One goal when designing integrated circuit (“IC”) chips is to optimize the power distribution in order to minimize voltage drops within the IC and to ensure that each component or portion of the chip (e.g., transistors, functional circuit blocks, etc.) is supplied with the optimum supply voltage. Another goal is to ensure that various components of the IC operate at the desired time in accordance with clock signal pulses.
Power supply voltages and clock signal pulses are typically supplied to an IC from an external power supply source through interconnect or bond pads on the IC. The power supply for the various components of the IC and clock signals to the desired components are routed from the interconnect or bond pads through metal conductors or other suitable wiring, collectively referred to herein as “traces.” Typically, a trace carries either a power supply or a clock signal, but not both.
Traces may be formed on or in one or more layers of the IC for both horizontal and vertical power or clock signal distribution in a variety of patterns that may be regular or irregular in shape. Additionally, the traces on or in the various levels of an IC may vary in material as well as in width, diameter, and even length depending on the pattern. Accordingly, the resistive load caused by a trace in one path to a particular component of the IC (such as transistors, functional circuit blocks, etc.) may be different than the resistive load caused by a trace(s) in another distribution path.
Typical digital ICs include a large number of clocked components such as flip-flops, registers, latches, and the like that change state in response to clock signal pulses. It is desirable to synchronize state changes for groups of such IC components by tying them to the same clock signal. To this end, the IC typically employs a clock tree or branching network of conductors and buffers to synchronize all components that are clocked to a particular clock signal.
Once the IC chip has been designed, and the locations of the clocked components are known in the IC layout, a clock tree synthesis tool (CTS tool) can be used to automatically generate a distributed clock network (referred to as a clock tree) for providing clock signals to the desired components. Generating the clock tree can include laying out the conductors or traces that distribute the clock signals to the desired components, typically in a manner which tries to ensure that the clock signals reach all desired components at the same time. Differences in arrival times of each clock signal pulse among the components that are clocked together is referred to as “skew.”
After the clock tree has been generated and the traces laid out, skew between components that are clocked together can be minimized or “balanced.” The CTS tool can typically be used to balance the clock tree by placing buffers in selected branches of the clock tree to adjust the delay of the clock signal along that clock tree branch or signal path. Buffers typically accomplish this by increasing or decreasing the rate at which the capacitance of clock tree conductors downstream from the buffer are charged, depending on the size and composition of the buffer used in a particular clock tree branch. Thus, the CTS tool can select the number, location, size, capacitive loading, composition, etc. of the buffers used to minimize skew to an acceptable level for the IC.
However, such clock tree generating and balancing difficulties are compounded in advanced IC design, such as the various “system on a chip” designs or application specific integrated circuits (“ASICs”), including stacked-die ICs. Designers have to generate and balance the clock tree, not just for clocked components on one chip for such advanced designs, but potentially across several chips, while at the same time meeting the clocking performance requirements of the stacked-die IC. This is a task for which most conventional CTS tools are not equipped.
Accordingly, what is needed is a system and method that can easily and effectively analyze clock distribution networks for stacked-die ICs using conventional single-die analysis tools.